1. Field of the Invention
The present invention relates to a high-voltage (HV) metal-oxide-semiconductor (MOS) transistor device and a manufacturing method thereof, and more particularly, to a HV MOS transistor device used for reducing leakage current and a manufacturing method thereof.
2. Description of the Prior Art
Double diffused drain metal-oxide-semiconductor (DDDMOS) transistor has both planar structure and high voltage-endurance ability, which is able to have better integration with the manufacturing method of standard complementary transistor device, and thus the DDDMOS transistor has become a common high-voltage device, and has been widely applied to high-voltage operating environments, such as power supplies for CPU, power managing systems, AC/DC converters or high-bandwidth power amplifiers.
The drain of the conventional DDDMOS transistor is formed by an ion implantation process and a thermal drive-in process using the gate and the spacer as a mask, and is designed to be a heavily doped region formed in a drift region with less doping concentration as compared with the heavily doped region, so the drift region can be used to tolerate high voltage from the drain. However, with minimization of the size of the transistor, the width of the spacer formed by advanced manufacturing processes becomes thinner and thinner, and thus the drain is much closer to the gate. As a result, the leakage current (from drain to base) of the DDDMOS transistor when the transistor in the off state is dramatically increased because of the gate induced drain current (GIDL) effect.
Therefore, it is a common goal in this field to provide a high-voltage (HV) metal-oxide-semiconductor (MOS) transistor device and a manufacturing method thereof to reduce the leakage current.